1. Field of the Invention
The present invention relates to semiconductor integrated circuits, and more particularly to output driver circuits (OCD) for integrated circuits.
2. Background Art
U.S. Pat. No. 5,659,261 issued Aug. 19, 1997 to Bacrania et al. entitled ANALOG-TO-DIGITAL CONVERTER AND OUTPUT DRIVER discloses an A-to-D converter including an output buffer with drivers that have pullup and pulldown transistors both coupled to an output. One of the transistors is connected to a first potential and the second transistor is connected to a second potential. A base drive circuit provides added current to saturate the pulldown transistor and thereby lower the collector-to-emitter voltage drop when the pulldown transistor is turned on.
U.S. Pat. No. 5,198,699 issued Mar. 30, 1993 to Hashimoto et al. entitled CAPACITOR-DRIVEN SIGNAL TRANSMISSION CIRCUIT discloses a switching circuit having its output connected to a transmission line. The switching circuit operates to couple a first capacitor to the switching circuit output in response to receiving an input signal of a first bit value. The switching circuit further operates to couple a second capacitor to the output in response to receiving an input signal of a second bit value. The bit value is thereby propagated into the transmission line.
U.S. Pat. No. 5,128,567 issued Jul. 7, 1992 to Tanaka et al. entitled OUTPUT CIRCUIT OF SEMICONDUCTOR INTEGRATED CIRCUIT WITH REDUCED POWER SOURCE LINE NOISE discloses an output circuit of an semiconductor integrated circuit having a plurality of output transistors with different current driving abilities and a plurality of delay means for driving the output transistors at different delay times.
U.S. Pat. No. 4,791,326 issued Dec. 13, 1988 to Vajdic et al. entitled CURRENT CONTROLLED SOLID STATE SWITCH discloses a current controlled switch that compensates for switching time variation. A compensated current source operates with a current mirror to set the switching current and control the peak switching current in the switch, thereby controlling the switching transition time.
U.S. Pat. No. 4,634,893 issued Jan. 6, 1987 to Craycraft et al. entitled FET DRIVER CIRCUIT WITH MASK PROGRAMMABLE TRANSMISSION RATES discloses a field effect transistor circuit that has different rates of change of the output signal depending on fabrication mask designation of selected transistors to be either depletion or enhancement type devices.
U.S. Pat. No. 3,988,616 issued Oct. 26, 1976 to Shimada entitled DRIVER CIRCUIT FOR LIQUID CRYSTAL DISPLAY USING INSULATED GATE FETS discloses a driver circuit that comprises an output circuit having depletion and enhancement type FETs connected in series. A control signal is supplied directly to the gate of the enhancement FET and, through an inverter, to the gate of the depletion FET to provide a push-pull driver circuit.